1. Field of the Invention
This invention relates to a method of manufacturing a Bi-MIS (Bipolar and Metal Insulator Semiconductor) semiconductor device and particularly to a method in which wide-bandgap material is utilized for emitter formation of the bipolar transistor of Bi-MIS semiconductor device. The gate electrode of the MIS FET of the Bi-MIS semiconductor device is simultaneously formed using the same material, resulting in a simplification of the manufacturing processes thereof.
2. Description of the Prior Art
As a structure of Bi-MIS semiconductor devices, a Bi-MOS semiconductor device is widely known, wherein a bipolar transistor and MOS (Metal Oxide Semiconductor) FET are formed on a silicon substrate, a silicon oxide film being utilized as an insulating film for a gate electrode of the MOS FET. The structure and manufacturing method thereof in the prior art are explained below using FIG. 1.
FIG. 1 shows a cross section of a Bi-MOS semiconductor device of the prior art. A p-type silicon substrate 1 is used, and an N.sup.+ -type buried layer 2 is formed, and next an n-type epitaxial layer 3 is grown thereon. The substrate surface is subjected to thermal oxidization forming a thin silicon oxide film and a silicon nitride layer is deposited by a CVD method (not shown). The silicon nitride layer is removed selectively except on the surface areas for the subsequent transistor forming area. Using the resist layer as a mask, a p.sup.+ -type isolation region 4 is formed by a boron ion implantation and then a collector pull out region 10 is formed by a phosphorous ion implantation.
A thick field oxide layer 9 is formed on isolation regions 4 by the thermal oxidization method known as LOCOS method. The silicon nitride layer and silicon oxide film on the transistor forming areas are removed and the silicon epitaxial layer 3 is exposed. In FIG. 1, area 5 shows a region where a bipolar transistor is formed in subsequent processes; and area 6, a p-channel MOS FET.
The substrate is subjected to a thermal oxidization, forming a thin silicon oxide film 16 in the transistor forming areas 5 and 6. A resist layer (not shown) is formed on the substrate having an opening for a base layer 7, and a boron ion implantation is performed forming the p-type base layer 7. After removing the above resist layer, the substrate is again covered with a new resist layer (not shown), and an opening for an emitter region is formed in the resist layer, and the silicon surface under the opening is exposed by removing the silicon oxide film 16 therein. The entire surface of the substrate is deposited with polysilicon by a CVD method, and then the polysilicon except in areas for an emitter electrode 21 and a gate electrode 17 is etched away.
A resist layer (not shown) is formed on the substrate and openings for a source and drain regions are formed therein. Again a boron ion implantation is performed, forming a p-type source region 14 and a p-type drain region 15, whereby the resist layer and the gate electrode 17 play a role as a mask for the boron ion implantation, and, therefore, the channel region of the MOS FET can be formed, auto-positioned, i.e., self-aligned with regard to the gate electrode.
A new resist layer (not shown) is formed on the substrate and an opening is formed for the area on the emitter electrode 21. An arsenic or phosphorous ion implantation is carried out. In order to form an n-type emitter layer 8, the emitter electrode 21 of doped polysilicon is then subjected to a heat treatment of about 980.degree. C., resulting in a thermal diffusion of n-type ions into the p-type base layer 7. This thermal treatment also plays a role of annealing or an activating function for source and drain regions 14 and 15, ion-implanted previously.
The entire surface of the substrate is CVD deposited, forming an insulating layer 23 (for example, silicon oxide layer or PSG layer), and contact holes are formed therein. A metal layer such as aluminum alloy is formed thereon, and is patterned, forming a collector electrode 11, an emitter wiring 12, a base electrode 13, a source electrode 19, a drain electrode 20, and a gate wiring 25.
The above fabrication method relating to the Bi-MOS structure of FIG. 1 shown in a schematically simplified form, is just one example among many methods. The method applied in forming the emitter layer 8 is suitable for obtaining a high speed bipolar transistor, wherein doped polysilicon is utilized. In order to manufacture a Bi-CMOS semiconductor device, wherein an n-channel MOS FET is added to the structure of FIG. 1, the processes such as a formation of a p-well in the epitaxial layer 3 and an n-type ion implantation for source and drain regions of the n-channel MOS FET are necessary. Usually, a channel cut is formed under the field oxide layer 9.
Further, an emitter layer 8 may be formed by a direct ion implantation into the base layer 7, however, a more precise control of the emitter region is enabled by the method described above using doped polysilicon for an emitter formation.
With a demand of high speed operation of the Bi-MIS semiconductor device, a higher transition frequency f.sub.t and a larger current amplification factor h.sub.FE are required in the bipolar transistor section and further a higher cut off frequency f.sub.c is required in the MIS FET section. The above prior method of using doped polysilicon and forming the emitter layer by thermal diffusion can achieve a more precise control of a pn junction between emitter and base layers than the method of direct As ion implantation into the emitter layer. However, the doped polysilicon method requires a subsequent heat treatment of higher than 950.degree. C. for diffusing the implanted ions into the contacting silicon crystal. This heat treatment has a bad influence on the source and drain regions of MIS FET, which have a high level of impurity doping such as 1.times.10.sup.19 /cm.sup.3 to 1.times.10.sup.20 /cm.sup.3. The source and drain regions spread in a lateral direction resulting in reducing the gate length L, i.e., the distance between source and drain regions, and in making it difficult to control the gate length precisely. The MIS FET is liable to such defects as fluctuation of threshold voltage, punch-through phenomenon, etc. On the other hand, when the source and drain regions are formed after formation of the emitter layer, a subsequent heat treatment for the source and drain regions causes the depth of the emitter layer to vary and makes it difficult to provide a precise value of f.sub.t.
In order to obtain a higher transition frequency f.sub.t and a larger current amplification factor h.sub.FE, another method has been developed in which a wide-bandgap material is used as an emitter material, the emitter being grown on a silicon monocrystal substrate and forming a heterojunction with a base layer in the silicon substrate. Such a transistor is conventionally called a wide-bandgap or wide-gap emitter transistor.